Descrição
Formal verification is a powerful new digital design method. In this cutting-edge tutorial, two of the field'apos;s best known authors team up to show designers how to efficiently apply Formal Verification, along with hardware description languages like Verilog and VHDL, to more efficiently solve real-world design problems.
Contents: Simulation-Based Verification * Introduction to Formal Techniques * Contrasting Simulation vs. Formal Techniques * Developing a Formal Test Plan * Writing High-Level Requirements * Proving High-Level Requirements * System Level Simulation * Design Example * Formal Test Plan * Final System Simulation
Contents: Simulation-Based Verification * Introduction to Formal Techniques * Contrasting Simulation vs. Formal Techniques * Developing a Formal Test Plan * Writing High-Level Requirements * Proving High-Level Requirements * System Level Simulation * Design Example * Formal Test Plan * Final System Simulation
Características
Peso | 0.00 Kg |
---|---|
Produto sob encomenda | Não |
Marca | McGraw-Hill Education, LLC (Prof C/S) (Livros Digitais) |
Número de Páginas | 240 (aproximado) |
Idioma | 337 |
Acabamento | e-book |
Territorialidade | Internacional |
Formato Livro Digital | |
Gratuito | Não |
Proteção Drm | Sim |
Tamanho do Arquivo | 1271 |
Início da Venda | 10/05/2005 |
Código do Formato | |
Cód. Barras | 9780071588898 |
Ano da Publicação | 2005 |
Autor | Perry,Douglas; Foster,Harry |