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Digit-Serial Computation (Cód: 6326031)

Richard Hartley; Keshab K. Parhi


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Digit-Serial Computation



The sampling rates for digital signal processing (DSP) in such applications as speech, telephony, mobile radio, video, radar and sonar, ranges from 10 kHz to 100 MHz. Real-time implementation of such systems
requires design of hardware that can process signal samples as these are received from the source, rather than storing them in buffers for batch-mode processing. Efficient implementation of DSP hardware demands a study of
families of architectures and styles, selecting an appropriate architecture for a specific application. Digit-Serial Computation is proposed as an appropriate design methodology when bit-serial systems
cannot meet sampling rate requirements, and where bit-parallel systems require excessive hardware. A family of implementations can be obtained by changing the digit size parameter, allowing an optimum trade-off between
throughput and size. Digit-Serial Computation describes the architecture, and the design and layout methods used in Parsifal: the silicon compiler developed at GEC's Corporate R&D
Laboratory. The structures architecture of digit-serial designs lends itself to automatic compilation from algorithmic descriptions. The book also goes on to discuss wider-ranging issues in digit-serial design in chapters
on `folding' and `unfolding', as well as in chapters on systolic arrays, canonic-signed-digit number representation and carry-save arithmetic. The book is an excellent source of reference and may be used as a
text for an advanced course on the subject.


Produto sob encomenda Sim
Cód. Barras 9780792395737
Altura 23.40 cm
I.S.B.N. 9780792395737
Profundidade 1.91 cm
Referência 9780792395737
Ano da edição 1995
Idioma Inglês
Número de Páginas 324
Peso 0.45 Kg
Largura 15.60 cm
AutorRichard Hartley; Keshab K. Parhi