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Verification Techniques for System-Level Design (Cód: 2891809)

Fujita, Masahiro; Prasad, Mukul; Ghosh, Indradeep

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Verification Techniques for System-Level Design

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Descrição

This book will explain how to verify SoC (Systems on Chip) logic designs using'quot;formal? and 'quot;semiformal? verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in 'quot;functional? verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.

For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.

• First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs.
• Formal verification of high-level designs (RTL or higher).
• Verification techniques are discussed with associated system-level design methodology.

Características

Peso 0.00 Kg
Produto sob encomenda Sim
Marca ELSEVIER S&T
Idioma 337
Acabamento e-book
Proteção Drm Sim
Tamanho do Arquivo 2055
Início da Venda 27/07/2010
Código do Formato Pdf
Cód. Barras 9780080553139
Ano da edição 12009
Ano da Publicação 110
AutorFujita, Masahiro; Prasad, Mukul; Ghosh, Indradeep